Decoder IC for F2F encoded magnetic stripe
CMOS integrated circuit with built-in operational amplification circuitry
Available for single, dual or triple track decoding solutions
Support 75/210 BPI recording density
Adjustable output clock pulse width 14 to 60 gs.
Ignore start bit selectable for 4 or 8 bits
Idle mode controllable by external hardware or Micro-Processor
Accept magnetic head data input frequency from 300 to 12600 bit/sec
Decoder IC for F2F encoded magnetic strip.
CMOS integrated circuit with built-in operational amplification circuitry
Available for single, dual or triple track decoding solutions
Support 75/210 BPI recording density
Adjustable output clock pulse width 14 to 60 gs.
Ignore start bit selectable for 4 or 8 bits
Idle mode controllable by external hardware or Micro-Processor
Accept magnetic head data input frequency from 300 to 12600 bit/sec
Integrated Amplification Circuit for magnetic head signal.
Both output polarities supported.
Adjustable read data output clock pulse width.
Triple channel and support for 75/210bpi recording density.
Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec.
Power-down stand-by mode to reduce current consumption.
11 leading bits ignored.
Enhanced noise filter.
Automatic offset voltage cancellation circuit for amplifiers.
Advanced algorithm to effectively read poor condition cards as well as high jitter cards
Integrated Amplification Circuit for magnetic head signal.
Both output polarities supported.
Adjustable read data output clock pulse width.
Triple channel and support for 75/210bpi recording density.
Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec.
Power-down stand-by mode to reduce current consumption.
Provide the option of 8 or 11 leading bits ignored.
Enhanced noise filter.
Automatic offset voltage cancellation circuit for amplifiers.
Advanced algorithm to effectively read poor condition cards as well as high jitter cards
Integrated amplification circuit for magnetic head signal.
QFN 24 pin package (Quad Flat No-lead): small footprint on PCB, only 4mm*4mm
Bi-directional data transfer protocol
Triple track and support for 75/210bpi recording density.
Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec.
Provide the option of 8 or 11 leading bits ignored
Enhanced noise filter
Automatic offset voltage cancellation circuit for amplifiers
Advanced algorithm to effectively read poor condition cards as well as high jitter cards
768-bit memory buffer for each track
Low Power Standby Mode when not reading.
Power saving shutdown mode.
Operation from 2.5 to 5.5V
Power consumption: 1.5mA (Operation @ 3.3V) , 1mA (Standby @3.3V) 50uA (Shutdown @3.3V)